Nowadays, many electronic devices incorporate functionality that operates at radio frequencies, such as mobile communication devices. The implementation of such functionality in a cost-effective manner is far from trivial. It is well-known that bipolar transistors are particularly suitable for handling signals in the radio frequency (RF) domain. However, the manufacture of integrated circuits (ICs) based on silicon bipolar transistor technology is more costly than for instance complementary metal oxide semiconductor (CMOS) ICs, and the downscaling of the device feature size is more easily achieved in CMOS technology. The cost-effective nature of CMOS technology has led to the acceptance of CMOS technology as the mainstream technology of choice for the manufacture of a wide variety of semiconductor components including ICs.
However, the breakdown characteristics of CMOS transistors limit the usefulness of CMOS transistors in RF applications unless costly measures are implemented in the CMOS process to improve these characteristics. Such costly measures typically prohibit the use of RF-CMOS technologies for manufacturing small volume devices such as analog mixed signal (AMS) devices. For these reasons, efforts have been made to produce bipolar transistors using a CMOS process flow, thereby providing mixed technology ICs in which bipolar transistors can be used for handling RF signals. An example of such an IC is provided in WO2010/066630 A1.
The challenge that process developers face is that the number of alterations to the CMOS process should remain small whilst at the same time yielding good quality bipolar transistors that are capable of handling high frequency signals. An example of a low-complexity IC including a heterojunction bipolar transistor formed in a CMOS process flow can for instance be found in WO 2003/100845 A1.
Nevertheless, the applicability of such CMOS technology-based bipolar transistors is not without problems. It is particularly difficult to manufacture several identical bipolar transistors that have relatively wide emitter areas. Wide emitter areas are needed for instance for bipolar transistors that must be capable of handling large currents. To create identical bipolar transistors process variations between different bipolar transistors on the same chip need to be minimized. The latter may for instance be required when implementing a current mirror, where the ratio between the two current sources has to be as precisely defined as possible to ensure reliable operation of the current mirror.
The main problem with establishing relatively large emitter areas, e.g. base windows having a width in excess of 2 μm is that during the planarizing of the emitter material deposited on the substrate with the purpose to fill the base window, not only excess emitter material is removed from outside the base window but also from inside the base window. This is known as dishing, and is particularly problematic when using chemical mechanical polishing (CMP). The CMP step typically stops at a polishing-resistant layer over the substrate such as a Si3N4 nitride layer. When increasing the dimensions (width or length) of the base window (it is noted that the dimensions of the base window govern the dimensions of the emitter), due to the relative softness of the emitter material such as poly-Si when planarizing the resultant structure after the poly-Si deposition in a CMP step, the dishing effect can become so pronounced for base windows having a width in excess of 2 μm that substantially all emitter material is removed from inside the base window.